YAXY: A New Hybrid FPGA-Based Hardware Acceleration of TFHE

Fully Homomorphic Encryption (FHE) enables direct computation on ciphertexts, thereby ensuring data privacy during processing. However, its widespread application is impeded by high computational costs, with bootstrapping being a critical efficiency bottleneck. Torus FHE (TFHE) facilitates efficient evaluation of arbitrary Boolean functions via fast gate bootstrapping. This paper proposes YAXY, an FPGA accelerated design for TFHE bootstrapping. It combines high level synthesis (HLS) and register-transfer level (RTL) optimizations to improve performance. Our approach employs parameterized key unrolling and pipelined key transmission at the HLS level, coupled with a hierarchically pipelined RTL architecture designed to maximize parallelism in external product computations. Implemented on the Xilinx ZCU102 platform at 300MHz, the design achieves a latency of 0.44ms and a throughput of 2,273 bootstrappings per second. It offers the lowest-latency standalone FPGA TFHE bootstrapping. Compared to processor-based implementations, our accelerator exhibits superior speed-resource tradeoff. The results validate that HLS-RTL co-design can significantly enhance the practicality of FHE for privacy-preserving applications.