Weight Bit Sensitivity Analysis and FPRH-Based Hardening Strategy for CNN Accelerators

This paper proposes a comprehensive quantitative analysis and hardening framework based on fault injection experiments to address the reliability issue of weight bit-flips in convolutional neural networks (CNNs) deployed on edge hardware accelerators. Through scripted bit-level fault injection into externally stored floating-pointhts, we systematically quantify the bit sensitivity of weights across different neural network layers. Experimental results show that bit flips in high-order exponent bits are the primary cause of mean Average Precision (mAP) degradation. Based on these findings, we propose a novel hardening algorithm (FPRH), which innovatively integrates a fixed-bit redundancy mechanism combining Triple Modular Redundancy (TMR) and Dual Modular Redundancy (DMR). This algorithm achieves an approximate 7% improvement in mAP with only a 0.5% overhead in inference time, providing a hardware-friendly solution to enhance the single-event upset (SEU) resilience of CNNs.