Voltage Error Compensation Strategy for High-Speed SRM Drives using Five-Segment Switching Pattern

To address the problem of output voltage lag in switched reluctance motors (SRM) drives caused by the discrete modulation mode, This paper proposes a voltage error suppression strategy using five-segment modulation. The strategy begins with the introduction of a control region boundary prediction algorithm. It is designed to predict the ideal voltage output waveform based on discrete sampling signals. Considering that the five-segment switching pattern can reduce current ripple induced by voltage harmonics, this paper presents a combination of the switching pattern with the predicted voltage output waveform. This approach not only considers the limitations on the number of level outputs in five-segment switching pattern but also ensures the accuracy of the reference voltage from the current controller. By predicting the ideal voltage waveform in advance, the proposed strategy can effectively eliminate the time-lag problem in the conventional modulation. Finally, the effectiveness of the proposal in enhancing torque output capability under high-speed conditions is demonstrated through experiments on a 6kW 12/8 SRM experimental platform.