VLSI implementation of a high-speed and low-power punctured viterbi decoder

Qiao Li; Yuxin You; Jinxiang Wang; Yizheng Ye

VLSI implementation of a high-speed and low-power punctured viterbi decoder

Qiao Li^*
, Yuxin You
, Jinxiang Wang
, Yizheng Ye

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumptions, the unnecessary computations of path metric are omitted in add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in survivor-memory-unit (SMU). The decoding latency of (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185mW with 200Mb/s throughput using 0.25μm CMOS technology.

Original language	English
Title of host publication	TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1205-1208
Number of pages	4
ISBN (Print)	0780374908
State	Published - 2002
Event	2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, TENCOM 2002 - Beijing, China Duration: 28 Oct 2002 → 31 Oct 2002

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume	2
ISSN (Print)	2159-3442
ISSN (Electronic)	2159-3450

Conference

Conference	2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, TENCOM 2002
Country/Territory	China
City	Beijing
Period	28/10/02 → 31/10/02

Keywords

Punctured Viterbi decoder
VLSI

Cite this

Li, Q., You, Y., Wang, J., & Ye, Y. (2002). VLSI implementation of a high-speed and low-power punctured viterbi decoder. In TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering (pp. 1205-1208). (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2). Institute of Electrical and Electronics Engineers Inc..

Li, Qiao ; You, Yuxin ; Wang, Jinxiang et al. / VLSI implementation of a high-speed and low-power punctured viterbi decoder. TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 1205-1208 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).

@inproceedings{5e35be6eff8e4d7090b65e7dac944e66,

title = "VLSI implementation of a high-speed and low-power punctured viterbi decoder",

abstract = "This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumptions, the unnecessary computations of path metric are omitted in add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in survivor-memory-unit (SMU). The decoding latency of (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185mW with 200Mb/s throughput using 0.25μm CMOS technology.",

keywords = "Punctured Viterbi decoder, VLSI",

author = "Qiao Li and Yuxin You and Jinxiang Wang and Yizheng Ye",

year = "2002",

language = "英语",

isbn = "0780374908",

series = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1205--1208",

booktitle = "TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering",

address = "美国",

note = "2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, TENCOM 2002 ; Conference date: 28-10-2002 Through 31-10-2002",

}

Li, Q, You, Y, Wang, J & Ye, Y 2002, VLSI implementation of a high-speed and low-power punctured viterbi decoder. in TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1205-1208, 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, TENCOM 2002, Beijing, China, 28/10/02.

VLSI implementation of a high-speed and low-power punctured viterbi decoder. / Li, Qiao; You, Yuxin; Wang, Jinxiang et al.
TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. Institute of Electrical and Electronics Engineers Inc., 2002. p. 1205-1208 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - VLSI implementation of a high-speed and low-power punctured viterbi decoder

AU - Li, Qiao

AU - You, Yuxin

AU - Wang, Jinxiang

AU - Ye, Yizheng

PY - 2002

Y1 - 2002

N2 - This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumptions, the unnecessary computations of path metric are omitted in add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in survivor-memory-unit (SMU). The decoding latency of (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185mW with 200Mb/s throughput using 0.25μm CMOS technology.

AB - This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumptions, the unnecessary computations of path metric are omitted in add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in survivor-memory-unit (SMU). The decoding latency of (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185mW with 200Mb/s throughput using 0.25μm CMOS technology.

KW - Punctured Viterbi decoder

KW - VLSI

UR - https://www.scopus.com/pages/publications/0038309882

M3 - 会议稿件

AN - SCOPUS:0038309882

SN - 0780374908

T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON

SP - 1205

EP - 1208

BT - TENCOM 2002 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, TENCOM 2002

Y2 - 28 October 2002 through 31 October 2002

ER -

VLSI implementation of a high-speed and low-power punctured viterbi decoder

Abstract

Publication series

Conference

Keywords

Other files and links

Fingerprint

Cite this