VLSI design of inverse scan and inverse quantisation for MPEG-2 decoder

This paper presents a new architecture style for the design of inverse scan and inverse quantisation for MPEG-2 video decoder, based on the description of their algorithm according to MPEG-2 standard. For inverse quantisation, a modified partial product generator based on Modified Booth's Algorithm is introduced, and the partial products are summed up by Wallace tree. The design implementation is described in high level RTL (register transfer level) code, which is completely technology independent and can be easily converted from one technology to another. For the verification purpose, the core, synthesized by 0.35μm CMOS cells library, costs only 2,800 gates when it works in 80 MHz. Therefore, it can be used in MPEG-2 video decoder operating in real time.