@inproceedings{ec4807ecb1aa4416876309f84d974b65,
title = "VLSI design and implementation of high-speed Viterbi decoder",
abstract = "This paper presents a new architecture for high-speed Viterbi decoder with low power dissipation based on the modified T-algorithm and modified trace-back methods. The former algorithm is used to reduce the unnecessary operations in path metric computation, while the latter is adopted to reuse the already generated trace-back routes to reduce the times of trace-back operations, so the power consumption can be saved. High throughput and short decoding latency are achieved by parallel computation in the add-compare-select unit and pipeline structure in the survivor-memory-unit. The complexity of the (2,1,7) Viterbi decoder is about 50,000 gates with a decoding latency of 32 clock cycles, and an area of 3.88 mm2 including IO pad with a throughput of 200 Mb/s using 0.25 μm technology.",
keywords = "Decoder, T-algorithm, Trace-back, Viterbi",
author = "You, \{Yu Xin\} and Wang, \{Jin Xiang\} and Lai, \{Feng Chang\} and Ye, \{Yi Zheng\}",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 1st International Conference on Communications, Circuits and Systems, ICCCAS 2002 ; Conference date: 29-06-2002 Through 01-07-2002",
year = "2002",
doi = "10.1109/ICCCAS.2002.1180573",
language = "英语",
series = "2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "64--68",
editor = "Lemin Li",
booktitle = "2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings",
address = "美国",
}