Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns

Weiguang Sheng; Liyi Xiao; Zhigang Mao

doi:10.1109/PRDC.2008.9

Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns

Weiguang Sheng^*
, Liyi Xiao
, Zhigang Mao

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation of soft error mitigation mechanisms of the circuits. This paper outlines the characteristics of a new fault-injection platform HSECT-SPI (HIT Soft Error Characterization Toolkit-Spice Based) and its evaluation in some benchmark circuits implemented with distinct processes and soft error hardening techniques. It also details some techniques devised and implemented within the platform to automate and speed-up the circuit level fault-injection experiments. Experimental results are provided, showing that the platform is efficient, accurate and can direct the design of soft error immune circuits with at least three orders of magnitudes speed gain.

Original language	English
Title of host publication	Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008
Pages	17-23
Number of pages	7
DOIs	https://doi.org/10.1109/PRDC.2008.9
State	Published - 2008
Event	14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008 - Taipei, Taiwan, Province of China Duration: 15 Dec 2008 → 17 Dec 2008

Publication series

Name	Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008

Conference

Conference	14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008
Country/Territory	Taiwan, Province of China
City	Taipei
Period	15/12/08 → 17/12/08

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10.1109/PRDC.2008.9

Cite this

Sheng, W., Xiao, L., & Mao, Z. (2008). Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns. In Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008 (pp. 17-23). Article 4725274 (Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008). https://doi.org/10.1109/PRDC.2008.9

@inproceedings{d4413ea9302e45f99d681e281049cbd0,

title = "Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns",

abstract = "Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation of soft error mitigation mechanisms of the circuits. This paper outlines the characteristics of a new fault-injection platform HSECT-SPI (HIT Soft Error Characterization Toolkit-Spice Based) and its evaluation in some benchmark circuits implemented with distinct processes and soft error hardening techniques. It also details some techniques devised and implemented within the platform to automate and speed-up the circuit level fault-injection experiments. Experimental results are provided, showing that the platform is efficient, accurate and can direct the design of soft error immune circuits with at least three orders of magnitudes speed gain.",

author = "Weiguang Sheng and Liyi Xiao and Zhigang Mao",

year = "2008",

doi = "10.1109/PRDC.2008.9",

language = "英语",

isbn = "9780769534480",

series = "Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008",

pages = "17--23",

booktitle = "Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008",

note = "14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008 ; Conference date: 15-12-2008 Through 17-12-2008",

}

Sheng, W, Xiao, L & Mao, Z 2008, Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns. in Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008., 4725274, Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, pp. 17-23, 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, Taipei, Taiwan, Province of China, 15/12/08. https://doi.org/10.1109/PRDC.2008.9

Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns. / Sheng, Weiguang; Xiao, Liyi; Mao, Zhigang.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008. 2008. p. 17-23 4725274 (Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation of soft error mitigation mechanisms of the circuits. This paper outlines the characteristics of a new fault-injection platform HSECT-SPI (HIT Soft Error Characterization Toolkit-Spice Based) and its evaluation in some benchmark circuits implemented with distinct processes and soft error hardening techniques. It also details some techniques devised and implemented within the platform to automate and speed-up the circuit level fault-injection experiments. Experimental results are provided, showing that the platform is efficient, accurate and can direct the design of soft error immune circuits with at least three orders of magnitudes speed gain.

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Sheng W, Xiao L, Mao Z. Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns. In Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008. 2008. p. 17-23. 4725274. (Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008). doi: 10.1109/PRDC.2008.9

Versatile and efficient techniques for speeding-up circuit level simulated fault-injection campaigns

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