VeriRepair: Toward Reliable LLM-Based RTL Repair via CoT-Supervised Multi-Objective Fine-Tuning and Hybrid Retrieval

Ensuring the reliability of Register-Transfer Level (RTL) designs is critical, yet automated Verilog repair remains challenging due to requirements on synthesizability, timing correctness, and functional consistency. Existing LLM-based approaches rely on heuristic prompting, lack structured reasoning, and are trained on narrow datasets, which limits generalization and leads to logically inconsistent fixes. We present VeriRepair, the firsta novel framework to introduce Chain-of-Thought (CoT) supervision into hardware repair, combined multi-objective fine-tuning with a hybrid retrieval-augmented inference mechanism. We construct a 13k-pair RTL bug-fix dataset, covering more than 40 error types across six categories and enriched with reasoning annotations. The model is jointly fine-tuned on repaired code and reasoning traces, yielding more accurate and interpretable fixes. During inference, a hybrid retriever leverages semantic and structural similarity to guide patch generation. Experiments demonstrate that VeriRepair attains 76.6% Top-1 accuracy, surpassing VeriDebug by 20.1% and CirFix by 44.9%. Moreover, the framework is readily deployable in real industrial flows, integrating with pre-synthesis lint/fix pipelines and simulation- or UVM-based verification. The dataset is open source and available on GitHub: https://github.com/90ICEDA/verirepair.