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TPSTA: A Tissue P System-Inspired Task Allocator for Heterogeneous Multi-Core Systems

  • Yuanhan Zhang
  • , Zhenzhou Ji*
  • *Corresponding author for this work
  • School of Computer Science and Technology, Harbin Institute of Technology
  • School of Computer Science and Technology (School of Software), Harbin Institute of Technology Weihai

Research output: Contribution to journalArticlepeer-review

Abstract

Heterogeneous multi-core systems (HMCSs) typically face a dilemma: heuristics (e.g., Linux CFS) are fast but blind to global constraints, while meta-heuristics (e.g., GAs) are globally optimal but too slow for real-time OS interaction. To bridge this gap without relying on “black-box” neural networks, we introduce the Tissue P System-Inspired Task Allocator (TPSTA). By mapping HMCS and parallel task scheduling to Tissue P System models and vectorized linear algebra problems, TPSTA achieves a computational complexity of (Formula presented.), effectively compressing the decision space. Our rigorous evaluation across four dimensions reveals a system strictly bound by physical constraints rather than algorithmic heuristics. (1) Under sufficient resource provisioning (four chips), TPSTA achieves a 0.00% Deadline Miss Ratio (DMR). Crucially, stress tests on constrained hardware (two chips) show graceful degradation to a 12.88% DMR, matching the optimal theoretical bound of EDF, whereas standard heuristics collapse to failure rates > 68%. On a massive 4096-core cluster, TPSTA outperforms the Linux GTS scalar baseline by 14.4×, maintaining low latency where traditional algorithms fail (>8 s). (3) Adaptability: The system demonstrates adaptive routing in handling hardware heterogeneity; without explicit rule-coding, it autonomously prioritizes data locality during NUMA transfers and migrates compute-bound tasks during thermal throttling events. (4) Physical Limits: Finally, our roofline analysis confirms that while the algorithmic speedup is theoretically linear, practical performance saturates at ~375× due to the Memory Wall, validating the isomorphism between synaptic bandwidth and hardware memory channels.

Original languageEnglish
Article number1339
JournalElectronics (Switzerland)
Volume15
Issue number6
DOIs
StatePublished - Mar 2026
Externally publishedYes

Keywords

  • hard real-time constraints
  • heterogeneous multi-core scheduling
  • membrane computing
  • tissue-like P systems
  • vectorized parallelism

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