Thermal Resistance Network Modeling Method Based on Chip Layered Structure

Three-dimensional packaging technology is constantly advancing, and more and more functional devices are being integrated into micrometer-scale spaces. This compresses overall temperature range that the system can withstand into an extremely small range, which raises higher demands for quick heat evaluation in the early stages of structural design. This paper proposes a method for modeling the thermal resistance network based on the chip layered structure, which describes the transient temperature variation during the bonding process. The method involves detailed modeling of the chip packaging structure, dividing nodes according to material differences and dimensional parameters of each layer. It analyzes the heat transfer paths and constructs the network accordingly. Additionally, the thermal performance of the packaging structure is abstracted into thermal resistance and thermal capacitance, with the RC circuit characteristics being used to simulate the temperature variation when the structure is subjected to heat. Through this thermal resistance model, the influence of structural dimensions and materials on heat transfer characteristics is studied. The findings indicate that while changing the substrate thickness can control the temperature difference, it also carries the risk of bonding failure. In contrast, changing the distance from the chip to the bonding surface proves to be a more effective and reliable approach. Additionally, the model accuracy was verified using ANSYS finite element simulation. The results show that, compared to the finite element solution, the temperature analysis error at the target points is at most 4.17%, demonstrating that the thermal resistance network model accurately reflects the transient temperature variation of the structure under heating. The research presented in this paper provides a fast and precise method for node temperature analysis, which is of significant importance for improving the efficiency of early-stage dimensional parameter design of microsystem packaging structures.