Thermal aware floor planning timing optimal method for buffer insertion

With the integration degree of integrated circuit (IC) is increasingly high, the heat on a chip is also growing, which leads to an uneven temperature distribution intra-die and affects the propagation delay of the critical path thereby affecting the performance of buffer insertion path. A buffer insertion timing optimization method which considered the heat distribution condition optimization floor-planning was proposed. It estimates the temperature and heat distribution of chip in the early stages of layout design and is applied to layout optimization floor-planning. The thermal aware floor planning based on simulated annealing algorithm was used to adjust and optimize planning, and then we made an optimization for timing by proposed buffer insertion model and fast buffer insertion algorithm. Simulation results show that the use of the proposed buffer insertion delay optimization method can effectively reduce the worst delay and the number of buffer insertion, worst delay is 9%-18% lower than traditional methods, 5%-7% lower than the best method shown in reference, and the insertion buffer numbers are 10 to 20 less than its.