The sleep transistor sizing in DSTN power gating circuits

A novel technique is proposed to estimate the maximum instantaneous current (MIC) in distributed sleep transistor network (DSTN) power gating circuits. Firstly, the parameters of the standard cells in the circuits are extracted and the MICs of the cells are calculated. Then the timing and placement information of the cells are processed to estimate the MICs of the clusters in the circuit. Through this proposed method the obtained MIC result is tighter and the runtime is reduced. With the estimated MICs, annealing algorithm is firstly used to do sleep transistor sizing, as well as heuristic algorithm and heuristic algorithm with λ. Experimental results show that the average area overhead can be reduced to less than 1%. Finally, we verify sleep transistor sizing results by SPICE simulations and voltage drop on the virtual ground line meets well with the constraint of 5% V _dd.