The reduction of leading- and trailing-edge of high-voltage steep pulse in plasma immersion ion implantation

During plasma immersion ion implantation (PHI) processes, due to the capacitance effect of the coaxial cable and plasma load, the output voltage pulse of high-voltage modulator possesses a longer leading- and trailing-edge time. The leading- and trailing-edge of the high voltage (HV) pulse have a critical effect on the ion-energy uniformity, depth and dose distribution during PHI processes. In this work, a tetrode was used as a hard tube to switch the DC high voltage, and a HV pulse modulator with a maximum pulse voltage of 40 kV was built successfully. The effect of the trailing-edge time on the implantation uniformity was simulated by one-dimension PIC method. The potential on the control grids of the tetrode was optimized to obtain a HV pulse with a short rise time. In our system, 200 V potential on grid one is utilized and the leading-edge time of pulse can be as small as 1 μs. The IGBTs in series was utilized to release the remnant charges reserved in the equivalent capacitance of the plasma load and coaxial cable. Thus the trailing-edge time of the HV pulse could be reduced. The effect of the driver signals with different delay time and the absorption parameters of each IGBTs were simulated by PSPICE software to optimize the design the electric circuit.