The influence of interconnect layer cavity size, position, and shape on the thermal resistance of power devices

With the increase in packaging density of power devices, heat dissipation of power devices has gradually become research hotspots. Among them, the most critical structure that affects the heat dissipation of power devices is the chip interconnect layer. The presence of cavity in the interconnect layer can increase the thermal resistance of the device and reduce its heat dissipation performance. This paper uses finite element numerical simulation method to establish a three-dimensional finite element model of TO247 packaged SiC device. Then, the interconnect layer cavity models of different sizes and positions were defined, and the temperature fields of the different devices during operating were calculated to reveal the influence of cavities on the thermal resistance of the device. The dual interface method was used to conduct thermal resistance testing on devices containing cavity defects, and the results showed that the measured values were consistent with the simulation calculations, indicating that the simulation model can be used to explore the influence of thermal resistance on defective devices. The research results indicate that as the cavity rate of the chip interconnect layer increases, the thermal resistance of the device also increases. When the total cavity rate is the same, the relationship between the thermal resistance of the device corresponding to different positions of cavities is as follows: central cavity>corner cavity. In addition, compared to circular and rectangular cavity, distributed cavities can effectively reduce the device's thermal resistance.