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The FPGA implementation of IP core of PD attitude controller for small satellites

  • Yu Ye Ding*
  • , Sheng Chang Lan
  • , Yi Hua
  • , Meng Li Li
  • , Rui Pan
  • , Guo Dong Xu
  • *Corresponding author for this work
  • School of Electronics and Information Engineering, Harbin Institute of Technology
  • Harbin Institute of Technology

Research output: Contribution to journalArticlepeer-review

Abstract

In the sight of the higher requirement about operation speed and control accuracy in satellite attitude control system, this paper analyzed the feasibility of PD attitude controller by using FPGA, and proposed a method using the input enable and the output control symbol to dominate the internal calculation module to figure out the problem of data synchronization. The paper used hardware description language to achieve the function of each module, and finally instantiated the IP core of PD controller. The result shows that the design is able to accomplish the calculation of attitude control torque by only using 34 clock pulses and the accuracy of control can reach 10-5 magnitude. The speed and accuracy meet the needs of the modern small satellite control system and lay the foundation for using FPGA implementation in small satellite attitude control system.

Original languageEnglish
Pages (from-to)40-45
Number of pages6
JournalHarbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology
Volume44
Issue number9
StatePublished - Sep 2012

Keywords

  • Control law of PD
  • Core of IP
  • FPGA
  • Satellite attitude control

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