The design of parallelized BCH codec

Chenxu Wang; Yuhong Gao; Liang Han; Jinxiang Wang

doi:10.1109/CISP.2010.5646178

The design of parallelized BCH codec

Chenxu Wang^*
, Yuhong Gao
, Liang Han
, Jinxiang Wang

^*Corresponding author for this work

Harbin Institute of Technology Weihai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Based on the characteristics of Flash memory, this paper introduces a parallel linear feedback shift register to implement the coder and parallel Chien search circuit to make up the decoder. The BM algorithm, using Newton's equation, is used to get the error location polynomial, thus making it possible to get error location by Chien search. The parallel BCH codec discussed in this paper has advantage in higher error-correcting capability and can be configured for three different error-correcting capabilities. So it can be used many situations. In addition, shorted code is choosed to speed up Chien search progresses in this paper. At last, the decode speed and the error probability is analyzed. The whole design has been realized and verified with Verilog HDL.

Original language	English
Title of host publication	Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010
Pages	3057-3059
Number of pages	3
DOIs	https://doi.org/10.1109/CISP.2010.5646178
State	Published - 2010
Externally published	Yes
Event	2010 3rd International Congress on Image and Signal Processing, CISP 2010 - Yantai, China Duration: 16 Oct 2010 → 18 Oct 2010

Publication series

Name	Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010
Volume	7

Conference

Conference	2010 3rd International Congress on Image and Signal Processing, CISP 2010
Country/Territory	China
City	Yantai
Period	16/10/10 → 18/10/10

Keywords

BCH
Chien
LFSR
Parallelization

Access to Document

10.1109/CISP.2010.5646178

Cite this

@inproceedings{f1900f64adf744c2b90484681fb500a4,

title = "The design of parallelized BCH codec",

abstract = "Based on the characteristics of Flash memory, this paper introduces a parallel linear feedback shift register to implement the coder and parallel Chien search circuit to make up the decoder. The BM algorithm, using Newton's equation, is used to get the error location polynomial, thus making it possible to get error location by Chien search. The parallel BCH codec discussed in this paper has advantage in higher error-correcting capability and can be configured for three different error-correcting capabilities. So it can be used many situations. In addition, shorted code is choosed to speed up Chien search progresses in this paper. At last, the decode speed and the error probability is analyzed. The whole design has been realized and verified with Verilog HDL.",

keywords = "BCH, Chien, LFSR, Parallelization",

author = "Chenxu Wang and Yuhong Gao and Liang Han and Jinxiang Wang",

year = "2010",

doi = "10.1109/CISP.2010.5646178",

language = "英语",

isbn = "9781424465149",

series = "Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010",

pages = "3057--3059",

booktitle = "Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010",

note = "2010 3rd International Congress on Image and Signal Processing, CISP 2010 ; Conference date: 16-10-2010 Through 18-10-2010",

}

Wang, C, Gao, Y, Han, L & Wang, J 2010, The design of parallelized BCH codec. in Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010., 5646178, Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010, vol. 7, pp. 3057-3059, 2010 3rd International Congress on Image and Signal Processing, CISP 2010, Yantai, China, 16/10/10. https://doi.org/10.1109/CISP.2010.5646178

The design of parallelized BCH codec. / Wang, Chenxu; Gao, Yuhong; Han, Liang et al.
Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010. 2010. p. 3057-3059 5646178 (Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010; Vol. 7).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - The design of parallelized BCH codec

AU - Wang, Chenxu

AU - Gao, Yuhong

AU - Han, Liang

AU - Wang, Jinxiang

PY - 2010

Y1 - 2010

N2 - Based on the characteristics of Flash memory, this paper introduces a parallel linear feedback shift register to implement the coder and parallel Chien search circuit to make up the decoder. The BM algorithm, using Newton's equation, is used to get the error location polynomial, thus making it possible to get error location by Chien search. The parallel BCH codec discussed in this paper has advantage in higher error-correcting capability and can be configured for three different error-correcting capabilities. So it can be used many situations. In addition, shorted code is choosed to speed up Chien search progresses in this paper. At last, the decode speed and the error probability is analyzed. The whole design has been realized and verified with Verilog HDL.

AB - Based on the characteristics of Flash memory, this paper introduces a parallel linear feedback shift register to implement the coder and parallel Chien search circuit to make up the decoder. The BM algorithm, using Newton's equation, is used to get the error location polynomial, thus making it possible to get error location by Chien search. The parallel BCH codec discussed in this paper has advantage in higher error-correcting capability and can be configured for three different error-correcting capabilities. So it can be used many situations. In addition, shorted code is choosed to speed up Chien search progresses in this paper. At last, the decode speed and the error probability is analyzed. The whole design has been realized and verified with Verilog HDL.

KW - BCH

KW - Chien

KW - LFSR

KW - Parallelization

UR - https://www.scopus.com/pages/publications/78650554218

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DO - 10.1109/CISP.2010.5646178

M3 - 会议稿件

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SN - 9781424465149

T3 - Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010

SP - 3057

EP - 3059

BT - Proceedings - 2010 3rd International Congress on Image and Signal Processing, CISP 2010

T2 - 2010 3rd International Congress on Image and Signal Processing, CISP 2010

Y2 - 16 October 2010 through 18 October 2010

ER -

The design of parallelized BCH codec

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Keywords

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