The design of delay pulse circuit for ultrasonic phased array system

This paper presents the development of delay pulse circuit with 1ns resolution for both driving ultrasonic array transducers and digital receive beamforming for ultrasonic phased array system. The circuit which can supply pulses with a 1ns time resolution employs the phase shifting with phase locked loop (PLL). In this way, 6 phase clocks with 1ns phase difference are generated, which are used to drive channel counters. Delay pulses of each channel are generated by counter. Based on this circuit, a design of digital receive beamforming with 1ns delay resolution is also presented. The design adopts a phase shifting technique of PLL to generate six clocks with 6ns periods and 1ns phase difference, which are selected as a non-uniform sampling clock to drive the A/D Converters according to the receive focal points. The delay pulse circuit is built with low-cast Field-programmable-gate-array (FPGA) components. By employing the novel architecture, the circuit has been achieved in FPGA. The simulation results are compared with two programmable delay chips and show that the proposed architecture achieves satisfactory performance for pulse delay.