@inproceedings{85987506e23f4a0f9d2facaf53a6b155,
title = "The configurable and high-performance architecture design of 2D in-place IDWT in JPEG2000",
abstract = "A multi-level 2D-IDWT's architecture with high performance and memory efficiency is proposed. The proposed architecture is composed of two 1D-IDWT cores and one single rearrangement register. Both the 1D-IDWT cores take only one multiplier delay in their critical path at the throughput rate of one-input/one-output. The single register, rather than traditional 1.5N transposing memory, is used to complete rearrangement task. The pipeline architecture of 2D-IDWT takes only one multiplier in the critical path. Moreover,the proposed architecture reduces 27\% on-chip memory(only need 2N for 53-IDWT and 4N for 97-IDWT) by utilizing the proposed alternate scanning method and decreases 20\% off-chip memory by applying the proposed memory map strategy without any performance loss.",
author = "Jinheng Han and Song Lu and Jinxiang Wang and Weizhe Xu and Fangfa Fu",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 ; Conference date: 28-10-2014 Through 31-10-2014",
year = "2014",
month = jan,
day = "23",
doi = "10.1109/ICSICT.2014.7021503",
language = "英语",
series = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Jia Zhou and Ting-Ao Tang",
booktitle = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",
address = "美国",
}