@inproceedings{4a69d4964acd458db667a0517d383cdc,
title = "Testability design based on relevance of circuit nodes and fault diagnosis",
abstract = "As an important part of electronic products and systems, the fault prediction and health management of board-level circuits has attracted wide attention and the testability design is the basis of the related studies. In this paper, a new method of testability design based on the correlation of circuit nodes is proposed and used to realize the selection of test points in a high-voltage power supply. First of all, all nodes in the circuit are grouped based on correlation analysis, and then calculate the distance between the fault class according to the existing fault data to select the test points of the circuit. Finally, extract the fault features of the selected test points and diagnose the fault. The results verifies the effectiveness of the proposed method in this paper.",
keywords = "board-level circuits, fault diagnosis, selection of test points, testability design",
author = "Liying Chen and Guofu Zhai and Xuerong Ye and Kaixin Zhang and Wei Zhao",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 8th IEEE Prognostics and System Health Management Conference, PHM-Harbin 2017 ; Conference date: 09-07-2017 Through 12-07-2017",
year = "2017",
month = oct,
day = "20",
doi = "10.1109/PHM.2017.8079296",
language = "英语",
series = "2017 Prognostics and System Health Management Conference, PHM-Harbin 2017 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Bin Zhang and Yu Peng and Haitao Liao and Datong Liu and Shaojun Wang and Qiang Miao",
booktitle = "2017 Prognostics and System Health Management Conference, PHM-Harbin 2017 - Proceedings",
address = "美国",
}