Test structure with variable test data width of IP cores for multicore SoCs with DVS and multiple voltage islands

Dynamic voltage scaling (DVS) is usually combined with partitioning the system into multiple voltage islands (MVI) to further lower dynamic power consumption, and it is widely adopted in SoC design nowadays. However, it brings great challenges with test. Different from SoC with only single voltage level, multi-Vdd SoCs must be tested at multiple voltage settings, which increases test time and test cost seriously. In addition, testing at lower voltage settings requires much more time because lower scan frequencies must be used for shifting test data using scan chains, and it results in an obvious waste of TAM bandwidth. In this paper, we propose a new test structure with variable test data width of IP cores which is mainly consisted of bandwidth conversion modules and an improved IJTAG network. This new test structure can fully utilize the TAM bandwidth by improving the test data width of IP cores with increasing the number of balanced scan chains, and it use the bandwidth conversion module to lower the frequency of test data using scan chains. Experimental results for a revised d695 from ITC'02 Test benchmarks highlight the effectiveness of the proposed test structure.