Test set compaction for combinational circuit based on compact genetic algorithm

As the increasing of digital circuit integration level and complexity, the test set size grows rapidly. In this paper, a new test compaction algorithm based on compact genetic algorithm for combinational circuits is presented. Compact genetic algorithm has the ability of global searching, and only needs two individuals for evolution. So compact genetic algorithm can deal with large scale test set compaction and consume less computing resources. The results of experiments on the ISC AS-85 benchmark circuits show that, the proposed method can get smaller test set than other similar methods.