Test pattern generation based on multi-TRC scan architecture for reducing test cost

Continuous scan-based design is an effective approach of reducing test application time in a system-on-a-chip (SoC) test architecture. However, two problems that are becoming quite critical for conventional continuous scan-based testing are large test data storage and high test power consumption. In order to mitigate two problems, this paper proposed a multi-Twisted ring counter scan architecture (MTRC-SA) based on multiple clock disabling (MCD) technique. Our approach firstly partition inputs into several compatible sets (CS) with the same size and one incompatible set (ICS). Test patterns are then generated by configurating CS/ICS into a TRC. The TRCs corresponding to CSs are utilized to invert their previous states, and the TRC corresponding to ICS is utilized to compress test data corresponding to ICS by TRC compression algorithm. Experimental results for the International Symposium on Circuits and Systems (ISCAS) 89 benchmark circuits show that significant reduction on test storage, test application time and power dissipation can be achieved compared to the conventional scan method and MCD.