Synthesis scheme for low power designs with multiple supply voltages by simulated annealing

In this paper, a Simulated Annealing method based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector and have got it by many iterations under the controlled temperature. The advantage of this algorithm is that it can avoid local optimization and converge whole optimization. Experiments with a number of DSP benchmarks show that the proposed algorithm is effective for low power design.