Suppression of Beat Phenomenon for Electrolytic Capacitorless Motor Drives Accounting for Sampling Delay of DC-Link Voltage

Beat phenomenon is an important issue for the practical application of electrolytic capacitorless motor drives. In this study, the characteristics of stator current harmonics caused by the voltage sampling delay are analyzed. Further, the beat phenomenon generated from the interaction between the harmonics and the fundamental currents is investigated, and the envelope feature of the stator current is derived mathematically. For the purpose of suppressing the beat phenomenon, a voltage reconstruction strategy is proposed to reduce the influence of dc-link voltage sampling delay at the six times of grid frequency. By utilizing the reconstructed dc-link voltage for calculation of PWM duty ratio, the beat phenomenon can be attenuated significantly. The proposed method can be integrated into motor control system easily. Experimental results show the effectiveness of the proposed strategy in a prototype of electrolytic capacitorless permanent magnet synchronous motor drive.