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Study of Chip Integration Process and Cooling Enhancement Based on BN-Filled Through-Silicon Vias

  • Jinchang Meng
  • , Shixiao Zhao
  • , Shuchang Fan
  • , Ningqiang Shi
  • , Ling Li*
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work reports a method to fill silicon via holes with ultra-high thermal conductivity Boron Nitride (BN) nanosheet materials (particle size leqslant 10 μm). The thermal conductivity of the filled silicon vias is 146.177 W/(mċ K), which is about 57.29% higher than that of the unfilled silicon vias. Utilizing the ultra-high thermal conductivity of BN and the thermal expansion coefficient that matches with that of Si, the thermal conductivity of the silicon vias can be effectively improved, which provides a new idea and methodology in the field of thermal management of three-dimensional integrated circuits.

Original languageEnglish
Title of host publication2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages425-429
Number of pages5
ISBN (Electronic)9798331542283
DOIs
StatePublished - 2024
Event2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024 - Harbin, China
Duration: 21 Nov 202422 Nov 2024

Publication series

Name2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024

Conference

Conference2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024
Country/TerritoryChina
CityHarbin
Period21/11/2422/11/24

Keywords

  • BN
  • Through-Silicon Vias
  • cooling enhancement
  • filling process

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