Structure design of data buffer for high-speed exchange devices

Along with the rapid increase of Internet bandwidth and the development of Internet applications, gigabit and ten-gigabit exchange devices are applied widely. The high performance structure of high-speed data buffer is a key to break throughput rate necklace. We provide a new design of multi-level buffer structure based on Field Programmable Gates Array (FPGA) by internal RAMs combined with external RAMs. Corresponding parallel schedule algorithm increases transmission speed and process ability. By improving pipeline, this structure can be applied for more high-speed environments.