Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm

Soft errors caused by particle strike in combinational circuits are a major concern in the design of reliable circuits. Particle strike induced single event transient (SET), especially the evolutional single event multiple transients (SEMTs) in nanoscale CMOS technologies, has been the non-negligible reliability issue for hardening design of combinational circuits. This paper presents a low overhead method to protect combinational circuits against particle strike. This method is made up of a combination of two sub-method: (1) a soft error sensitivity estimation method, called Layout-Based Multiple Event Probability Propagation (LBMEPP) and (2) a protection method based on gate sizing, called Intelligent optimization-Based Gate Sizing (IOBGS). Unlike the previous techniques that either overlook the SEMTs event or exploit fault injection. LBMEPP can provide the sensitivity estimation of combinational circuits in the presence of SET and SEMTs. The SEMTs adjacent cells are identified by the cell's layout and Geant4 Monte Carlo simulation. Therefore, the SEMTs event can be considered in the sensitivity estimation. Using the estimation result of LBMEPP, IOBGS adopts multi-objective particle swarm optimization algorithm to dynamically allocate and adjust each logical cells. In IOBGS, SER, circuit area and longest path delay of the circuit are selected as the optimization goals. The experiments conducted on several typical circuits show that the proposed optimization method can evidently decrease the SER with a limited overhead.