SoC test architecture design based on bandwidth matching

The reuse of intellectual property (IP) cores reduces the design cycle of system-on-a-chip (SoC), which is the main stream technology in modern integrated circuit (IC) design. The test architecture is emerged because test data can not be transferred to IPs directly through SoC pins. Traditional test architecture works at a frequency provided by automatic test equipment (ATE). The procedure of testing an IP core is: shifting in a test stimulus to the IP core scan chain, launching the test in one capture cycle, and shifting the test response out while shifting in the next test stimulus. However, this architecture has many shortcomings, such as the number of ATE channels does not match the best bandwidth to test the IPs in SoC. Therefore, a test architecture based on bandwidth matching is proposed in this paper, in which a bandwidth matching module is used to adjust the width and frequency of the test data, and to shorten the test time, which requires extra test area though. Experiment results on ITC'02 benchmark show the availability of the proposed method.