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Simultaneous multithreading trace processors

  • K. F. Wang*
  • , Zhenzhou Ji
  • , Mingzeng Hu
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

Abstract

In this paper, we propose a new next generation high-performance micro-architecture based on the combination of simultaneous multithreading and trace processor. By exploiting both Instruction-Level Parallelism and Thread-Level Parallelism, Simultaneous Multithreading Trace Processor can be expected to achieve higher performance than SMT or Trace Processor individual. We describe the organization of SMT Trace Processor architecture and some fundamental techniques. A path-based multiple traces prediction mechanism is also described in the paper.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsXingming Zhou, Ming Xu, Stefan Jahnichen, Jiannong Cao
PublisherSpringer Verlag
Pages96-103
Number of pages8
ISBN (Print)3540200541, 9783540200543
DOIs
StatePublished - 2003

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2834
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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