TY - GEN
T1 - Segmented Channel Modeling and Implementation for Deep Space Communications with Solar Scintillation
AU - Li, Yuliang
AU - Feng, Bowen
AU - Zhang, Zhikai
AU - Wang, Xunze
AU - Zhang, Qinyu
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper introduces a segmented channel modeling approach that not only expands the channel model to cover distances within 20 times the radius of the Sun in the deep-space segment but also utilizes a more comprehensive TDL model in the near-Earth segment. Furthermore, we utilize FPGA and software-defined radio (SDR) for the verification of the channel model. The FPGA implementation (50MHz) executes all channel modules by using hardware circuits and reduces channel computation time to only 6.1% compared to software simulations (8 cores, 3.2GHz), which significantly speeds up the computing. Moreover, the SDR implementation, which is built on the FPGA's computational foundation, incorporates RF hardware to achieve more realistic link simulations. The results from these hardware implementations closely align with theoretical predictions, affirming their utility for real-time simulation of deep space channels in laboratory conditions.
AB - This paper introduces a segmented channel modeling approach that not only expands the channel model to cover distances within 20 times the radius of the Sun in the deep-space segment but also utilizes a more comprehensive TDL model in the near-Earth segment. Furthermore, we utilize FPGA and software-defined radio (SDR) for the verification of the channel model. The FPGA implementation (50MHz) executes all channel modules by using hardware circuits and reduces channel computation time to only 6.1% compared to software simulations (8 cores, 3.2GHz), which significantly speeds up the computing. Moreover, the SDR implementation, which is built on the FPGA's computational foundation, incorporates RF hardware to achieve more realistic link simulations. The results from these hardware implementations closely align with theoretical predictions, affirming their utility for real-time simulation of deep space channels in laboratory conditions.
KW - FPGA
KW - channel simulator
KW - deep space channel
KW - hardware implementation
KW - segmented channel modeling
UR - https://www.scopus.com/pages/publications/85206475372
U2 - 10.1109/ICCC62479.2024.10682018
DO - 10.1109/ICCC62479.2024.10682018
M3 - 会议稿件
AN - SCOPUS:85206475372
T3 - 2024 IEEE/CIC International Conference on Communications in China, ICCC 2024
SP - 1352
EP - 1357
BT - 2024 IEEE/CIC International Conference on Communications in China, ICCC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE/CIC International Conference on Communications in China, ICCC 2024
Y2 - 7 August 2024 through 9 August 2024
ER -