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Research on synchronous sampling clock jitter of power system

  • Harbin Institute of Technology Shenzhen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The principle of synchronous sampling is introduced and the sampling noise brought by clock jitter is analyzed in this paper. The method of calculating the SNR of sampling signal interfered by clock jitter is proposed and the condition that clock jitter noise can be neglected is derived too. This paper proposes a kind of equal phase mean filter fitting for clock jitter noise. The effects of this filter with different amount of points are compared. The simulation result shows that equal phase mean filtering can attenuate clock jitter noise effectively.

Original languageEnglish
Title of host publication2nd International Conference on Information Engineering and Computer Science - Proceedings, ICIECS 2010
DOIs
StatePublished - 2010
Externally publishedYes
Event2nd International Conference on Information Engineering and Computer Science, ICIECS 2010 - Wuhan, China
Duration: 25 Dec 201026 Dec 2010

Publication series

Name2nd International Conference on Information Engineering and Computer Science - Proceedings, ICIECS 2010

Conference

Conference2nd International Conference on Information Engineering and Computer Science, ICIECS 2010
Country/TerritoryChina
CityWuhan
Period25/12/1026/12/10

Keywords

  • Clock jitter
  • Equal phase mean filter
  • Power system
  • Synchronous sampling

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