Research on Dead Time Compensation of Parallel Multilevel Topology Structure

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Inverter dead time compensation algorithm has always been a hot spot in the field of motor control. Parallel multi-level topology inverters can achieve the goals of high switching frequency and high power through the parallel connection of power devices, and are widely used in motor simulators and power systems. This article first quantifies the cause of the output waveform distortion of the three-phase voltage inverter, and derives the error voltage formula due to the non-ideal characteristics of the inverter under the parallel multi-level structure based on this. Finally, based on the determined parallel multi-level topology, an accurate dead-zone compensation scheme is proposed. Simulations verify the effectiveness of the dead-zone compensation strategy proposed in this paper to suppress the output voltage and current harmonics.

Original languageEnglish
Title of host publicationProceedings - International Conference on Control Science and Electric Power Systems, CSEPS 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages190-193
Number of pages4
ISBN (Electronic)9781665426183
DOIs
StatePublished - May 2021
Externally publishedYes
Event2021 International Conference on Control Science and Electric Power Systems, CSEPS 2021 - Shanghai, China
Duration: 28 May 202130 May 2021

Publication series

NameProceedings - International Conference on Control Science and Electric Power Systems, CSEPS 2021

Conference

Conference2021 International Conference on Control Science and Electric Power Systems, CSEPS 2021
Country/TerritoryChina
CityShanghai
Period28/05/2130/05/21

Keywords

  • dead time compensation
  • output waveform distortion
  • parallel multi-level topology

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