Regulating SMT resource allocation via thread-sensitive register renaming

SMT processors generally regulate the resource allocation indirectly by controlling the Instruction-Fetch(I-Fetch) process, which may lead to resource misuse and even starvation, incurring resource underutilization and performance depression. Various improving techniques have been proposed; however their effects are discounted due to either being too expensive to implement, or failing in eliminating the imbalance of resource allocation. This paper proposes a novel scheme, Thread-Sensitive Register Renaming (TSRR), which serves as a resource gating, remarkably eliminating the imbalance of resource allocation and improving the overall performance. TSRR features that: (1) it tracks the performance variations and dynamically tunes the resource amount available to each thread, realizing allocation-on-demand, (2) it is cost-effective because it tunes up all resources just by regulating the allocation of the rename-register-file (RRF), and (3) concerning both effectiveness and fairness, TSRR prevents both resource misuse and starvation, whereas fully exploits the performance potential of each thread. Meanwhile, TSRR can lessen the RRF size demands and I-Fetch hardware complexities.