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RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory

  • School of Electronics and Information Engineering, Harbin Institute of Technology

Research output: Contribution to journalArticlepeer-review

Abstract

As 3-D nand flash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.

Original languageEnglish
Pages (from-to)2165-2175
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume34
Issue number7
DOIs
StatePublished - 1 Jul 2026
Externally publishedYes

Keywords

  • Error correction
  • nand flash memory
  • page-aware bit mapping
  • polar code

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