Pipelined Parallel Design of SIFT Algorithm on FPGA

Yuanhao Zhang; Tianliang Xu; Jianfeng Li; Zhenbin Lv; Shanqiang Yang; Chenxu Wang; Yuhang Wang; Bo Chu; Zhiwei Han

doi:10.1109/ASICON66040.2025.11325887

Pipelined Parallel Design of SIFT Algorithm on FPGA

Yuanhao Zhang
, Tianliang Xu
, Jianfeng Li
, Zhenbin Lv
, Shanqiang Yang
, Chenxu Wang^*
, Yuhang Wang
, Bo Chu
, Zhiwei Han

^*Corresponding author for this work

Harbin Institute of Technology Weihai
Weihai
Ltd.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an FPGA-accelerated architecture for real-time Scale-Invariant Feature Transform (SIFT) algorithm implementation. To address the high computational complexity of the algorithm, we design a pyramid structure with reduced layers but maintained high feature point generation rate, implement a threshold-based extreme point detection circuit, replace division operations with multiply-add units in descriptor normalization, and realize a fully pipelined circuit architecture. Experimental results on the Xilinx Kintex-7 XC7K325T platform demonstrate that our design achieves a processing speed of 3.19ms/frame for 640×480 images, reaching a 115.4× speedup over CPU implementation while preserving feature matching accuracy.

Original language	English
Title of host publication	2025 IEEE 16th International Conference on ASIC, ASICON 2025
Publisher	IEEE Computer Society
ISBN (Electronic)	9798331539177
DOIs	https://doi.org/10.1109/ASICON66040.2025.11325887
State	Published - 2025
Externally published	Yes
Event	2025 IEEE 16th International Conference on ASIC, ASICON 2025 - Kunming, China Duration: 21 Oct 2025 → 24 Oct 2025

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	2025 IEEE 16th International Conference on ASIC, ASICON 2025
Country/Territory	China
City	Kunming
Period	21/10/25 → 24/10/25

Keywords

Scale-invariant feature transform
feature extraction
field-programmable gate array
hardware acceleration

Access to Document

10.1109/ASICON66040.2025.11325887

Cite this

@inproceedings{018a2c1700b9422da9c203a1eb9318c7,

title = "Pipelined Parallel Design of SIFT Algorithm on FPGA",

abstract = "This paper presents an FPGA-accelerated architecture for real-time Scale-Invariant Feature Transform (SIFT) algorithm implementation. To address the high computational complexity of the algorithm, we design a pyramid structure with reduced layers but maintained high feature point generation rate, implement a threshold-based extreme point detection circuit, replace division operations with multiply-add units in descriptor normalization, and realize a fully pipelined circuit architecture. Experimental results on the Xilinx Kintex-7 XC7K325T platform demonstrate that our design achieves a processing speed of 3.19ms/frame for 640×480 images, reaching a 115.4× speedup over CPU implementation while preserving feature matching accuracy.",

keywords = "Scale-invariant feature transform, feature extraction, field-programmable gate array, hardware acceleration",

author = "Yuanhao Zhang and Tianliang Xu and Jianfeng Li and Zhenbin Lv and Shanqiang Yang and Chenxu Wang and Yuhang Wang and Bo Chu and Zhiwei Han",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE 16th International Conference on ASIC, ASICON 2025 ; Conference date: 21-10-2025 Through 24-10-2025",

year = "2025",

doi = "10.1109/ASICON66040.2025.11325887",

language = "英语",

series = "Proceedings of International Conference on ASIC",

publisher = "IEEE Computer Society",

booktitle = "2025 IEEE 16th International Conference on ASIC, ASICON 2025",

address = "美国",

}

Zhang, Y, Xu, T, Li, J, Lv, Z, Yang, S, Wang, C, Wang, Y, Chu, B & Han, Z 2025, Pipelined Parallel Design of SIFT Algorithm on FPGA. in 2025 IEEE 16th International Conference on ASIC, ASICON 2025. Proceedings of International Conference on ASIC, IEEE Computer Society, 2025 IEEE 16th International Conference on ASIC, ASICON 2025, Kunming, China, 21/10/25. https://doi.org/10.1109/ASICON66040.2025.11325887

TY - GEN

T1 - Pipelined Parallel Design of SIFT Algorithm on FPGA

AU - Zhang, Yuanhao

AU - Xu, Tianliang

AU - Li, Jianfeng

AU - Lv, Zhenbin

AU - Yang, Shanqiang

AU - Wang, Chenxu

AU - Wang, Yuhang

AU - Chu, Bo

AU - Han, Zhiwei

PY - 2025

Y1 - 2025

N2 - This paper presents an FPGA-accelerated architecture for real-time Scale-Invariant Feature Transform (SIFT) algorithm implementation. To address the high computational complexity of the algorithm, we design a pyramid structure with reduced layers but maintained high feature point generation rate, implement a threshold-based extreme point detection circuit, replace division operations with multiply-add units in descriptor normalization, and realize a fully pipelined circuit architecture. Experimental results on the Xilinx Kintex-7 XC7K325T platform demonstrate that our design achieves a processing speed of 3.19ms/frame for 640×480 images, reaching a 115.4× speedup over CPU implementation while preserving feature matching accuracy.

AB - This paper presents an FPGA-accelerated architecture for real-time Scale-Invariant Feature Transform (SIFT) algorithm implementation. To address the high computational complexity of the algorithm, we design a pyramid structure with reduced layers but maintained high feature point generation rate, implement a threshold-based extreme point detection circuit, replace division operations with multiply-add units in descriptor normalization, and realize a fully pipelined circuit architecture. Experimental results on the Xilinx Kintex-7 XC7K325T platform demonstrate that our design achieves a processing speed of 3.19ms/frame for 640×480 images, reaching a 115.4× speedup over CPU implementation while preserving feature matching accuracy.

KW - Scale-invariant feature transform

KW - feature extraction

KW - field-programmable gate array

KW - hardware acceleration

UR - https://www.scopus.com/pages/publications/105034214167

U2 - 10.1109/ASICON66040.2025.11325887

DO - 10.1109/ASICON66040.2025.11325887

M3 - 会议稿件

AN - SCOPUS:105034214167

T3 - Proceedings of International Conference on ASIC

BT - 2025 IEEE 16th International Conference on ASIC, ASICON 2025

PB - IEEE Computer Society

T2 - 2025 IEEE 16th International Conference on ASIC, ASICON 2025

Y2 - 21 October 2025 through 24 October 2025

ER -

Pipelined Parallel Design of SIFT Algorithm on FPGA

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