Performance driven circuit clustering and partitioning

Ling Wang; Henry Selvaraj

doi:10.1109/ITCC.2002.1000414

Performance driven circuit clustering and partitioning

Ling Wang
, Henry Selvaraj

University of Nevada, Las Vegas

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.

Original language	English
Title of host publication	Proceedings - International Conference on Information Technology
Subtitle of host publication	Coding and Computing, ITCC 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	352-354
Number of pages	3
ISBN (Electronic)	0769515061, 9780769515069
DOIs	https://doi.org/10.1109/ITCC.2002.1000414
State	Published - 2002
Externally published	Yes
Event	International Conference on Information Technology: Coding and Computing, ITCC 2002 - Las Vegas, United States Duration: 8 Apr 2002 → 10 Apr 2002

Publication series

Name	Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002

Conference

Conference	International Conference on Information Technology: Coding and Computing, ITCC 2002
Country/Territory	United States
City	Las Vegas
Period	8/04/02 → 10/04/02

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Circuit testing
Clustering algorithms
Delay
Energy consumption
Field programmable gate arrays
Integrated circuit interconnections
Logic circuits
Logic testing
Minimization methods
Partitioning algorithms

Access to Document

10.1109/ITCC.2002.1000414

Cite this

Wang, L., & Selvaraj, H. (2002). Performance driven circuit clustering and partitioning. In Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002 (pp. 352-354). Article 1000414 (Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITCC.2002.1000414

@inproceedings{4c35626d154447d0a0522ca765a4b05a,

title = "Performance driven circuit clustering and partitioning",

abstract = "In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.",

keywords = "Circuit testing, Clustering algorithms, Delay, Energy consumption, Field programmable gate arrays, Integrated circuit interconnections, Logic circuits, Logic testing, Minimization methods, Partitioning algorithms",

author = "Ling Wang and Henry Selvaraj",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; International Conference on Information Technology: Coding and Computing, ITCC 2002 ; Conference date: 08-04-2002 Through 10-04-2002",

year = "2002",

doi = "10.1109/ITCC.2002.1000414",

language = "英语",

series = "Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "352--354",

booktitle = "Proceedings - International Conference on Information Technology",

address = "美国",

}

Wang, L & Selvaraj, H 2002, Performance driven circuit clustering and partitioning. in Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002., 1000414, Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002, Institute of Electrical and Electronics Engineers Inc., pp. 352-354, International Conference on Information Technology: Coding and Computing, ITCC 2002, Las Vegas, United States, 8/04/02. https://doi.org/10.1109/ITCC.2002.1000414

Performance driven circuit clustering and partitioning. / Wang, Ling; Selvaraj, Henry.
Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 352-354 1000414 (Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance driven circuit clustering and partitioning

AU - Wang, Ling

AU - Selvaraj, Henry

PY - 2002

Y1 - 2002

N2 - In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.

AB - In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.

KW - Circuit testing

KW - Clustering algorithms

KW - Delay

KW - Energy consumption

KW - Field programmable gate arrays

KW - Integrated circuit interconnections

KW - Logic circuits

KW - Logic testing

KW - Minimization methods

KW - Partitioning algorithms

UR - https://www.scopus.com/pages/publications/84949776482

U2 - 10.1109/ITCC.2002.1000414

DO - 10.1109/ITCC.2002.1000414

M3 - 会议稿件

AN - SCOPUS:84949776482

T3 - Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002

SP - 352

EP - 354

BT - Proceedings - International Conference on Information Technology

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Conference on Information Technology: Coding and Computing, ITCC 2002

Y2 - 8 April 2002 through 10 April 2002

ER -

Wang L, Selvaraj H. Performance driven circuit clustering and partitioning. In Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 352-354. 1000414. (Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2002). doi: 10.1109/ITCC.2002.1000414

Performance driven circuit clustering and partitioning

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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Cite this