Partitoning and placement with resources operating at multiple voltages

One promising technique to reduce the power consumption is to power the chip with multiple supply voltages. However, as noticed in [2], multiple voltage designs can cause a number of serious layout problems. We have shown that the layout problems can be partially solved by the addition of a partitioning step into the synthesis flow. A more subtle solution to solve the layout problems requires the placement be also included into the design flow. In this paper, we present a synthesis scheme, following a simulated annealing engine, to minimize power consumption and area with resources operating at multiple voltages under the timing constraints. The scheme considers any correlated factors, such as scheduling, binding, partitioning and placement, simultaneously to reduce power consumption due to both functional units and interconnections between and among them. Experiments with a number of DSP benchmarks show that the proposed algorithm can achieve significant reduction in power as well as area.