TY - GEN
T1 - Parterre
T2 - 5th International Conference on ASIC, ASICON 2003
AU - Mingyan, Yu
AU - Xuejun, Xie
AU - Jinxiang, Wang
AU - Yizheng, Ye
AU - Qingli, Zhang
AU - Chenxu, Wang
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - Product complexity combined with smaller products size and shorter time-to-market (TTM), requires an effective IC design methodology. System-on-Chip (SoC) designs provide integrated solutions to solve the problems. The paper presents an application-general SoC platform - Parterre, which includes three sub-platform: 3-bus sub- platform, IP verifying sub-platform, system debugging sub-platform. The 3-bus sub-platform is the kernel and foundation of the Parterre, and the other two are auxiliary sub-platform. The 3-bus sub-platform contains Integer Unit (IU), Floating-point Unit (FPU), Memory Management Unit (MMU) and three on-chip buses, etc. The IP verifying sub-platform is used to verify the IP blocks provided by third-party or designed by platform's owner, the system debugging sub-platform provides an environment of system debugging. The Lilac chip is also presented, which is derived from the Parterre platform, used to control aerocraft and manufactured using TSMC 0.25-μm CMOS technology.
AB - Product complexity combined with smaller products size and shorter time-to-market (TTM), requires an effective IC design methodology. System-on-Chip (SoC) designs provide integrated solutions to solve the problems. The paper presents an application-general SoC platform - Parterre, which includes three sub-platform: 3-bus sub- platform, IP verifying sub-platform, system debugging sub-platform. The 3-bus sub-platform is the kernel and foundation of the Parterre, and the other two are auxiliary sub-platform. The 3-bus sub-platform contains Integer Unit (IU), Floating-point Unit (FPU), Memory Management Unit (MMU) and three on-chip buses, etc. The IP verifying sub-platform is used to verify the IP blocks provided by third-party or designed by platform's owner, the system debugging sub-platform provides an environment of system debugging. The Lilac chip is also presented, which is derived from the Parterre platform, used to control aerocraft and manufactured using TSMC 0.25-μm CMOS technology.
UR - https://www.scopus.com/pages/publications/85085506912
U2 - 10.1109/ICASIC.2003.1277575
DO - 10.1109/ICASIC.2003.1277575
M3 - 会议稿件
AN - SCOPUS:85085506912
T3 - IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
SP - 413
EP - 416
BT - ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
A2 - Tang, Ting-Ao
A2 - Li, Wenhong
A2 - Yu, Huihua
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 21 October 2003 through 24 October 2003
ER -