Skip to main navigation Skip to search Skip to main content

Pareto based multi-objective mapping IP Cores onto NoC architectures

  • Wenbiao Zhou*
  • , Yan Zhang
  • , Zhigang Mao
  • *Corresponding author for this work
  • Harbin Institute of Technology Shenzhen
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a multi-objective exploration approach to map the IP cores onto the Network on Chip (NoC). The NoC mapping problem is treated as a two conflicting objective optimization problem of minimizing the average hop and achieving the thermal balance. Thus a set of Pareto-optimal mapping, instead of a single mapping, is an efficient solution. The proposed approach uses a novel representation and the multi-objective genetic algorithm capable of finding multiple Pareto-optimal solutions simultaneously for different performance requirement. Experimental results show the approach is highly efficient and accurate.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages331-334
Number of pages4
DOIs
StatePublished - 2006
Externally publishedYes
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 4 Dec 20066 Dec 2006

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/TerritorySingapore
Period4/12/066/12/06

Keywords

  • Low Power
  • Mapping
  • NoC
  • Thermal

Fingerprint

Dive into the research topics of 'Pareto based multi-objective mapping IP Cores onto NoC architectures'. Together they form a unique fingerprint.

Cite this