Abstract
In order to further reduce test data storage and test power of deterministic BIST based on scan slice overlapping, this paper proposes a novel optimization approach. Firstly, a san cell grouping method considering layout constraint is introduced to shorten the scan chain. Secondly, a novel scan cell ordering approach considering layout constraint is proposed to optimize the order of scan chain. Lastly, the authors propose an improved test pattern partition algorithm which selects the scan slice with the most specified bits as the first scan slice of the current overlapping block. Experimental results indicate that the proposed optimization approach significantly reduces the scan-in transitions and test data storage by 73%-93% and 60%-87%, respectively.
| Original language | English |
|---|---|
| Pages (from-to) | 43-56 |
| Number of pages | 14 |
| Journal | Journal of Electronic Testing: Theory and Applications (JETTA) |
| Volume | 27 |
| Issue number | 1 |
| DOIs | |
| State | Published - Feb 2011 |
Keywords
- Layout constraint
- Low-power testing
- Scan slice overlapping
- Scan-based design
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