Optimal schemes for ADC BIST based on histogram

Yong Sheng Wang; Jin Xiang Wang; Feng Chang Lai; Yi Zheng Ye

doi:10.1109/ATS.2005.86

Optimal schemes for ADC BIST based on histogram

Yong Sheng Wang^*
, Jin Xiang Wang
, Feng Chang Lai
, Yi Zheng Ye

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Scopus citations

Abstract

Two testing time reducing schemes of histogram-based BIST (Built-in Self Test) for testing of ADC IPs (Intellectual Propertys) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated.

Original language	English
Title of host publication	Proceedings - 14th Asian Test Symposium, ATS 2005
Pages	52-57
Number of pages	6
DOIs	https://doi.org/10.1109/ATS.2005.86
State	Published - 2005
Event	14th Asian Test Symposium, ATS 2005 - Calcutta, India Duration: 18 Dec 2005 → 21 Dec 2005

Publication series

Name	Proceedings of the Asian Test Symposium
Volume	2005
ISSN (Print)	1081-7735

Conference

Conference	14th Asian Test Symposium, ATS 2005
Country/Territory	India
City	Calcutta
Period	18/12/05 → 21/12/05

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10.1109/ATS.2005.86

Cite this

@inproceedings{7e91b12534f146ad8ecbd2bfdce0bbf0,

title = "Optimal schemes for ADC BIST based on histogram",

abstract = "Two testing time reducing schemes of histogram-based BIST (Built-in Self Test) for testing of ADC IPs (Intellectual Propertys) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated.",

author = "Wang, \{Yong Sheng\} and Wang, \{Jin Xiang\} and Lai, \{Feng Chang\} and Ye, \{Yi Zheng\}",

year = "2005",

doi = "10.1109/ATS.2005.86",

language = "英语",

isbn = "0769524818",

series = "Proceedings of the Asian Test Symposium",

pages = "52--57",

booktitle = "Proceedings - 14th Asian Test Symposium, ATS 2005",

note = "14th Asian Test Symposium, ATS 2005 ; Conference date: 18-12-2005 Through 21-12-2005",

}

TY - GEN

T1 - Optimal schemes for ADC BIST based on histogram

AU - Wang, Yong Sheng

AU - Wang, Jin Xiang

AU - Lai, Feng Chang

AU - Ye, Yi Zheng

PY - 2005

Y1 - 2005

N2 - Two testing time reducing schemes of histogram-based BIST (Built-in Self Test) for testing of ADC IPs (Intellectual Propertys) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated.

AB - Two testing time reducing schemes of histogram-based BIST (Built-in Self Test) for testing of ADC IPs (Intellectual Propertys) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated.

UR - https://www.scopus.com/pages/publications/33846936033

U2 - 10.1109/ATS.2005.86

DO - 10.1109/ATS.2005.86

M3 - 会议稿件

AN - SCOPUS:33846936033

SN - 0769524818

SN - 9780769524818

T3 - Proceedings of the Asian Test Symposium

SP - 52

EP - 57

BT - Proceedings - 14th Asian Test Symposium, ATS 2005

T2 - 14th Asian Test Symposium, ATS 2005

Y2 - 18 December 2005 through 21 December 2005

ER -

Optimal schemes for ADC BIST based on histogram

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