Noise analysis and characterization of a full differential CMOS interface circuit for capacitive closed-loop micro-accelerometer

To achieve a high precision capacitive closed-loop micro-accelerometer, a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit. This circuit consists of a balance-bridge module, a charge sensitive amplifier, a correlated-double-sampling module, and a logic timing control module. A special two-path feedback circuit configuration was given to improve the system linearity. The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit's noise, speed and accuracy. A detailed design method was given for this tradeoff. The noise performance optimized circuit has a noise root spectral density of 1.0 μV/√Hz, equivalent to rms noise root spectral density of 1.63 μg/√Hz. Therefore, the sensor's Brown noise becomes the main noise source in this design. This circuit is designed with 0.5 μm n-well CMOS process. Under a ±5 V supply, the Hspice simulation shows that the system sensitivity achieves 0.616 V/g, the system offset is as low as 1.456 mV, the non-linearity is below 0.03%, and the system linear range achieves ±5 g.