TY - GEN
T1 - Neural Network Based Threshold Voltage Model for 3D TLC NAND Flash
AU - Wei, Debao
AU - Qu, Jingyuan
AU - Song, Yu
AU - Zeng, Yanlong
AU - Qiao, Liyan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - With the rapid growth of technologies such as the cloud computing, file transfer, and others, the performance and capacity of storage devices are increasingly demanding. 3D NAND flash memory has emerged as a prominent non-volatile storage solution, characterized by its substantial storage capacity and superior performance. However, with the increase in bit density of flash memory, the reliability of flash memory becomes more and more serious. In this paper, a complete error characterisation test for three-dimensional (3D) trinary-level cell (TLC) flash memory is performed, with emphasis on the effects of retention loss, program/erase (P/E) wear, dwell time, and inter-layer variation on the threshold voltage Vth). Based on this, a complete flash memory threshold voltage dataset is constructed, and a BP neural network (BPNN) is employed to model the variation relationship of Vth for each logic state. Subsequently, the read reference voltage (RRV) is calibrated using the above model, and the optimized RRV is evaluated for its optimization effect on flash memory reliability. According to the experimental results, the RRV predicted by the neural network model closely matches the real optimal RRV, reducing the raw bit error rate (RBER) of the same flash memory model by up to 82.63%.
AB - With the rapid growth of technologies such as the cloud computing, file transfer, and others, the performance and capacity of storage devices are increasingly demanding. 3D NAND flash memory has emerged as a prominent non-volatile storage solution, characterized by its substantial storage capacity and superior performance. However, with the increase in bit density of flash memory, the reliability of flash memory becomes more and more serious. In this paper, a complete error characterisation test for three-dimensional (3D) trinary-level cell (TLC) flash memory is performed, with emphasis on the effects of retention loss, program/erase (P/E) wear, dwell time, and inter-layer variation on the threshold voltage Vth). Based on this, a complete flash memory threshold voltage dataset is constructed, and a BP neural network (BPNN) is employed to model the variation relationship of Vth for each logic state. Subsequently, the read reference voltage (RRV) is calibrated using the above model, and the optimized RRV is evaluated for its optimization effect on flash memory reliability. According to the experimental results, the RRV predicted by the neural network model closely matches the real optimal RRV, reducing the raw bit error rate (RBER) of the same flash memory model by up to 82.63%.
KW - Machine Learning
KW - NAND Flash
KW - Read reference voltage
KW - Storage reliability
UR - https://www.scopus.com/pages/publications/85174891001
U2 - 10.1109/ICEMI59194.2023.10270298
DO - 10.1109/ICEMI59194.2023.10270298
M3 - 会议稿件
AN - SCOPUS:85174891001
T3 - Proceedings of 2023 IEEE 16th International Conference on Electronic Measurement and Instruments, ICEMI 2023
SP - 125
EP - 132
BT - Proceedings of 2023 IEEE 16th International Conference on Electronic Measurement and Instruments, ICEMI 2023
A2 - Wu, Juan
A2 - Yin, Jiali
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE International Conference on Electronic Measurement and Instruments, ICEMI 2023
Y2 - 9 August 2023 through 11 August 2023
ER -