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Multiple DSC Filter-Based Three-Phase EPLL for Nonideal Grid Synchronization

  • Fengjiang Wu*
  • , Xiaoguang Li
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Contribution to journalArticlepeer-review

Abstract

This paper originally analyzes the effect of the harmonics, dc offsets, and unbalance on the three-phase enhanced phase-locked loop (3P-EPLL). It proves that 3P-EPLL is not able to accurately estimate the amplitude, phase angle, and frequency of the grid in such cases. In order to correctly estimate the grid synchronous information even under the nonideal grid conditions, an improved 3P-EPLL combined with the multiple delayed signal cancellation (DSC) filters is proposed. A DSC operator is set at the each input of 3P-EPLL to eliminate the input dc offsets and even-order harmonics. And the cascaded DSC (CDSC) module is plugged in both the frequency and amplitude loops to remove the effect of most of the odd-order harmonics and unbalance. The relationship between the delay constant of the DSC operator and the order of the harmonics hoping to eliminate is derived to design the structure of the CDSC module and determine the delay constant of each DSC operator in the CDSC module. Detailed experimental results of the standard 3P-EPLL and proposed one validate the theoretical analysis and the proposed phase-locked loop.

Original languageEnglish
Article number7919156
Pages (from-to)1396-1403
Number of pages8
JournalIEEE Journal of Emerging and Selected Topics in Power Electronics
Volume5
Issue number3
DOIs
StatePublished - Sep 2017

Keywords

  • DC offset
  • delayed signal cancelation (DSC)
  • harmonics
  • three-phase enhanced phase-locked loop (3P-EPLL)

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