Modeling of low-voltage oxide-based electric-double-layer thin-film transistors fabricated at room temperature

The room-temperature-made low-voltage electric-double-layer (EDL) thin-film transistors (TFTs) are reported previously with good performance including a huge EDL gate capacitance above 1 μF/cm². We report a two-dimensional simulation of the carrier transport and subgap density of states (DOS) in low-voltage indium tin oxide EDL TFTs. The simple model with a constant mobility and two-step subgap DOS reproduces well the characteristics of EDL TFTs. A nice fitting to the experimental data was obtained with a changeable effective conduction band DOS and valence band DOS model, which is reasonable to EDL electrostatic modulation mechanism. The EDL TFTs show much lower DOS than the InGaZnO₄ TFTs.