Mitigation Technique for Single Event Transient via Pulse Quenching

With the technology scaling down, the single event transients produced in the combinational circuit lead to an increasing threat to reliability. In this paper, Dummy Gate Enhanced Charge Sharing (DGECS) technique is proposed to mitigate single event transients, and enhances the pulse quenching of logic cells by increasing the charge sharing between key transistors. Mixed-mode 3-D technology computer aided design simulations were carried out with commercial 65nm dual-well CMOS technology. The simulation results show that the proposed layout technique can significantly reduce single event transient pulse widths and even completely quench transient pulses.