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Memory efficient soft error mitigation for CNN accelerators exploiting nonmonotonic bit sensitivity

  • Shanqiang Yang
  • , Jianfeng Li
  • , Guolin Yu
  • , Tianliang Xu
  • , Zhenbin Lv
  • , Chenxu Wang*
  • , Yuehong Gong
  • , Jinghao Chen
  • , Xinlei Su
  • *Corresponding author for this work
  • Harbin Institute of Technology
  • Harbin Institute of Technology Weihai
  • Shandong Provincial Key Laboratory of Marine Electronic Information and Intelligent Unmanned Systems
  • Shandong Jiaotong University

Research output: Contribution to journalArticlepeer-review

Abstract

Single-event upsets (SEUs) significantly threaten the reliability of convolutional neural network (CNN) accelerators in aerospace systems by corrupting the floating-point weights stored in memory. This paper systematically analyzes the bit-level sensitivity of IEEE 754 single-precision CNN weights through rigorous theoretical modeling and extensive fault injection experiments covering more than 150,000 trials. It proposes selective memory protection methods based on the identified sensitivity patterns. Our key finding reveals a previously unreported non-monotonic bit-sensitivity phenomenon, wherein certain middle exponent bits (b₂₆, b₂₅, b₂₄) exhibit higher error vulnerability compared to traditionally prioritized higher-order bits. This insight enables two innovative memory protection schemes targeting only the five most sensitive bits (b₃₁, b₃₀, b₂₆, b₂₅, b₂₄), reducing memory overhead from 200% to 31.25%, or even eliminating extra memory usage by embedding redundancy within low-sensitivity bits. These findings pave the way for developing highly reliable yet resource-efficient CNN accelerators tailored for severe radiation environments.

Original languageEnglish
Article number116106
JournalMicroelectronics Reliability
Volume180
DOIs
StatePublished - May 2026
Externally publishedYes

Keywords

  • Bit-level sensitivity analysis
  • CNN accelerator
  • Memory protection
  • Reliability
  • Single event upset
  • Soft error mitigation

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