LVDE: A Lightweight Threshold Voltage Distribution Estimation Strategy for High-Performance 3-D Nand Flash Memory

Low-density parity-check (LDPC) codes are now broadly employed as error correction code (ECC) solutions in NAND flash memories. With the rapid development of high-performance three-dimensional (3-D) NAND memories, mitigating the read latency caused by LDPC decoding attempts has emerged as an investigation focus. Existing investigations have demonstrated that efficient memory sensing is crucial to enhancing the efficiency of LDPC decoding attempts. The optimal memory sensing parameter options are determined by the threshold voltage distributions of NAND flash, which are difficult to be dynamically extracted during data retention. To address the issue, this article proposes an online lightweight strategy for threshold voltage distribution estimation, named LVDE. LVDE suggests a probe wordline design that uses one-read sampling to measure the threshold voltage distributions during long-term retention. Further, LVDE develops a methodology for the cross-layer estimation of threshold voltage distributions, thereby utilizing the measurements of the probe wordline to estimate those of each layer. LVDE is implemented on real flash chips to compare with numerous state-of-the-art strategies. Experimental results demonstrate that LVDE can significantly enhance the efficiency of LDPC decoding attempts and thus improve the read performance of 3-D NAND flash memory.