Low redundancy matrix-based codes for adjacent error correction with parity sharing

As CMOS technology scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one of the most challenging reliability issues for memories in space applications. In general, bits affected by MCUs are usually physically close. Error correction codes (ECCs) are commonly used to protect memory against MCUs. Recently, Matrix-based codes are an interesting option due to their low complexity decoding. The number of parity bits matrix-based codes required, which is related to the redundancy cells in memories, is not small. In this paper, a low redundancy scheme for matrix-based codes is presented. Based on a new matrix arrangement, the proposed scheme combines the extended Hamming codes per row and parity codes per column with parity sharing. Compared to the existing matrix-based codes, the proposed scheme maintains the same correction capability, but costs a smaller number of parity bits by 24% at most, a smaller area overhead by 16.24%, and a lower power overhead by 26.04%, which make the new scheme attractive for circuit implementations. Meanwhile, the MCUs probability of memories protected by the proposed scheme can be reduced owning to less redundancy memory cells. However, the delay required for the encoder and decoder of the proposed codes are in a middle level among the existing matrix-based codes, which results in that the proposed codes suit better for memories with a strict requirement of area and power.