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Low power hardware/software partitioning for multiprocessor SoC design

  • School of Computer Science and Technology, Harbin Institute of Technology

Research output: Contribution to journalArticlepeer-review

Abstract

An algorithm based on tabu search on a neural network was put forward to solve the low power hardware/software partitioning problem in design of system on chip (SoC) architectures consisting of several types of processors. The basic idea of it is: the refractory effect of inhibiting the repetitive firings is one of the characteristics of real biological neurons, which is similar to the tabu effect of tabu search, so tabu search can be realized by a neural network in which neurons inhibited by the refractory effect correspond to the tabu moves. With the complex dynamics of neural networks and excellent global search capacity of tabu search, the algorithm can effectively avoid trapping in undesirable local minima. The experiments for real task graphs show that the algorithm has better time performance than the genetic algorithm, and most of hardware/software partitioning solutions gotten from the algorithm possess the lower power consumption.

Original languageEnglish
Pages (from-to)991-996
Number of pages6
JournalGaojishu Tongxin/Chinese High Technology Letters
Volume17
Issue number10
StatePublished - Oct 2007
Externally publishedYes

Keywords

  • Hardware/software partitioning
  • Low power
  • Multiprocessor system-on-chip
  • Neural network
  • System level design
  • Tabu search

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